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NM24W04 Datasheet

  • NM24W04

  • 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM...

  • 108.46KB

  • 14頁(yè)

  • FAIRCHILD

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NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to V
CC
. The memory then becomes unalterable
unless WP is switched to V
SS
.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
s
Hardware Write Protect for entire memory
s
Low Power CMOS
200碌A(chǔ) active current typical
10碌A(chǔ) standby current typical
1碌A(chǔ) standby typical (L)
0.1碌A(chǔ) standby typical (LZ)
s
IIC Compatible interface
鈥?Provides bidirectional data transfer protocol
s
Sixteen byte page write mode
鈥?Minimizes total write time per byte
s
Self timed write cycle
鈥?Typical write cycle time of 6ms
s
Endurance: 1,000,000 data changes
s
Data retention greater than 40 years
s
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s
Available in three temperature ranges
- Commercial: 0擄 to +70擄C
- Extended (E): -40擄 to +85C
- Automotive (V): -40擄 to +125擄C
Block Diagram
VCC
VSS
WP
START CYCLE
SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
LOAD
A2
A1
A0
WORD
ADDRESS
COUNTER
INC
16/
32/
64/
128/
E2PROM
ARRAY
H.V. GENERATION
TIMING &CONTROL
SCL
XDEC
0/1/2/3
4
4
16
R/W
YDEC
Device Address Bits
CK
DIN
8
DOUT
DATA REGISTER
DS500074-1
漏 1999 Fairchild Semiconductor Corporation
NM24Wxx Rev. C.2
1
www.fairchildsemi.com

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