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NLSF1174/D Datasheet

  • NLSF1174/D

  • Hex D Flip-Flop with Common Clock And Reset

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  • ETC

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NLSF1174
Hex D Flip鈭扚lop with
Common Clock and Reset
This device consists of six D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of
the Clock input. Reset is asynchronous and active low. All
inputs/outputs are standard CMOS compatible.
Features
http://onsemi.com
MARKING
DIAGRAM
16
1
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Output Drive Compatibility: 10 LSTTL Loads
Outputs Directly Interface to CMOS
Operating Voltage Range: 2 to 6 V
Low Input Current: 1.0
mA
MSL Level 1
Chip Complexity: 162 FET
Q0
16
Reset
15
V
CC
14
Q5
13
QFN-16
MN SUFFIX
CASE 485G
SF
1174
ALYW
A
L
Y
W
12
D5
= Assembly Location
= Wafer Lot
= Year
= Work Week
D0
1
D1
2
11
D4
Q1
3
10
Q4
D2
4
9
D3
5
6
7
8
Q3
GND
Clock
Q2
Center pad on bottom may be connected to V
CC
of device.
This pad must be isolated or connected to V
CC
.
Figure 1. Pin Assignment (Top View)
FUNCTION TABLE
Inputs
Reset
L
H
H
H
H
L
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
No Change
No Change
漏
Semiconductor Components Industries, LLC, 2003
1
June, 2003 - Rev. 2
Publication Order Number:
NLSF1174/D

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