鈥?/div>
Extremely High Speed: t
PD
2.5 ns (typical) at V
CC
= 5 V
Designed for 2.3 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs
LVTTL Compatible 鈥?Interface Capability with 5 V TTL Logic with
V
CC
= 3 V
LVCMOS Compatible
24 mA Output Sink Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 72
LF
1
D
LF = Device Code
D = Date Code
PIN ASSIGNMENT
1
IN A1
1
8
V
CC
2
3
4
OUT Y3
2
7
OUT Y1
5
6
IN A2
3
6
IN A3
7
8
GND
4
5
OUT Y2
IN A1
OUT Y3
IN A2
GND
OUT Y2
IN A3
OUT Y1
V
CC
FUNCTION TABLE
Figure 1. Pinout
(Top View)
A Input
L
H
Y Output
Z
L
IN A1
IN A2
IN A3
1
1
1
OUT Y1
OUT Y2
OUT Y3
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
漏
Semiconductor Components Industries, LLC, 2001
1
September, 2001 鈥?Rev. 0
Publication Order Number:
NL37WZ06/D