鈥?/div>
Extremely High Speed: t
PD
2.0 ns (typical) at V
CC
= 5.0 V
Designed for 1.65 V to 5.5 V V
CC
Operation
Overvoltage Tolerant Inputs
LVTTL Compatible 鈥?Interface Capability with 5.0 V TTL Logic
with V
CC
= 3.0 V (2.7鈥?.3)
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability at V
CC
= 3.0 V
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 72; Equivalent Gate = 18
SC鈥?8/SOT鈥?63/SC鈥?0
DF SUFFIX
CASE 419B
MX
d
Pin 1
d = Date Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
IN A1
1
6
OUT Y1
GND
2
5
V
CC
IN A2
3
4
OUT Y2
Figure 1. Pinout
(Top View)
IN A1
IN A2
1
1
OUT Y1
OUT Y2
Figure 2. Logic Symbol
PIN ASSIGNMENT
1
2
3
4
5
6
IN A1
GND
IN A2
OUT Y2
V
CC
OUT Y1
FUNCTION TABLE
A Input
L
H
Y Output
L
H
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
漏
Semiconductor Components Industries, LLC, 2002
1
June, 2002 鈥?Rev. 0
Publication Order Number:
NL27WZ17/D