鈥?/div>
Extremely High Speed: t
PD
2.0 ns (typical) at V
CC
= 5 V
Designed for 2.3 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs
LVTTL Compatible 鈥?Interface Capability With 5 V TTL Logic with
V
CC
= 3 V
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 72; Equivalent Gate = 18
http://onsemi.com
MARKING
DIAGRAMS
SC鈥?8 / SOT鈥?63/SC鈥?0
DF SUFFIX
CASE 419B
MR
d
Pin 1
d = Date Code
IN A1
1
6
OUT Y1
TSOP鈥?/SOT鈥?3/SC鈥?9
DT SUFFIX
CASE 318G
Pin 1
MR
d
GND
2
5
V
CC
d = Date Code
IN A2
3
4
OUT Y2
Figure 1. Pinout
(Top View)
ORDERING INFORMATION
IN A1
IN A2
1
1
OUT Y1
OUT Y2
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
PIN ASSIGNMENT
1
2
3
4
5
6
IN A1
GND
IN A2
OUT Y2
V
CC
OUT Y1
FUNCTION TABLE
A Input
L
H
Y Output
L
H
漏
Semiconductor Components Industries, LLC, 2001
1
April, 2001 鈥?Rev. 1
Publication Order Number:
NL27WZ16/D