鈥?/div>
Extremely High Speed: t
PD
2.4 ns (typical) at V
CC
= 5.0 V
Designed for 1.65 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs
LVTTL Compatible 鈭?Interface Capability With 5.0 V TTL Logic
with V
CC
= 3.0 V
LVCMOS Compatible
24 mA Output Sink Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 72; Equivalent Gate = 18
Pb鈭扚ree Package is Available
MF
d
1
SC鈭?8
DF SUFFIX
CASE 419B
Pin 1
d = Date Code
MF
d
1
TSOP鈭?
DT SUFFIX
CASE 318G
Pin 1
d = Date Code
IN A1
1
6
OUT Y1
PIN ASSIGNMENT
1
GND
2
5
V
CC
2
3
4
5
IN A2
3
4
OUT Y2
6
IN A1
GND
IN A2
OUT Y2
V
CC
OUT Y1
FUNCTION TABLE
Figure 1. Pinout
(Top View)
A Input
L
H
IN A1
IN A2
1
1
OUT Y1
OUT Y2
Y Output
Z
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 2. Logic Symbol
漏
Semiconductor Components Industries, LLC, 2004
1
May, 2004 鈭?Rev. 4
Publication Order Number:
NL27WZ06/D