鈥?/div>
Tiny SOT鈭?53 and SOT鈭?53 Packages
Extremely High Speed: t
PD
2.5 ns (typical) at V
CC
= 5.0 V
Designed for 1.65 V to 5.5 V V
CC
Operation, CMOS Compatible
Over Voltage Tolerant Inputs V
IN
may be Between 0 and 7.0 V for
V
CC
Between 0.5 and 5.4 V
TTL Compatible 鈭?Interface Capability with 5.0 V TTL Logic with
V
CC
= 2.7 V to 3.6 V
LVCMOS Compatible
24 mA Output Sink Capability, Pullup may be between 0 and 7.0 V
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 20
Pb鈭扚ree Packages are Available
= Device Marking
= One Digit Date Code
PIN ASSIGNMENT
Pin
1
NC
1
OVT
IN A
2
5
V
CC
2
3
4
5
Function
NC
IN A
GND
OUT Y
V
CC
GND
3
4
OUT Y
FUNCTION TABLE
A Input
L
Y Output
Z
L
Figure 1. Pinout
(Top View)
H
IN A
1
ORDERING INFORMATION
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
漏
Semiconductor Components Industries, LLC, 2005
1
January, 2005 鈭?Rev. 3
Publication Order Number:
NL17SZ06/D