鈥?/div>
Tiny SOT鈭?53 and SOT鈭?53 Packages
2.4 ns T
PD
at 5 V (typ)
Source/Sink 24 mA at 3.0 V
Over鈭扸
oltage Tolerant Inputs
Pin For Pin with NC7SZ02P5X, TC7SZ02FU and TC7SZ02AFE
Chip Complexity: FETs = 20
Designed for 1.65 V to 5.5 V V
CC
Operation
Pb鈭扚ree Packages are Available
http://onsemi.com
MARKING
DIAGRAMS
5
1
SOT鈭?53/SC70鈭?/SC鈭?8A
DF SUFFIX
CASE 419A
d = Date Code
5
5
L3 D
1
SOT鈭?53
XV5 SUFFIX
CASE 463B
L3
D
1
5
L3
d
B
1
5
V
CC
1
A
2
= Device Marking
= One Digit Date Code
GND
3
4
Y
PIN ASSIGNMENT
Pin
1
Function
A
B
GND
Y
V
CC
Figure 1. Pinout
(Top View)
2
3
A
B
4
w1
Y
5
Figure 2. Logic Symbol
FUNCTION TABLE
Output
Input
A
L
L
H
H
B
L
H
L
H
Y=A
)
B
Y
H
L
L
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2005
1
January, 2005 鈭?Rev. 3
Publication Order Number:
NL17SZ02/D