鈥?/div>
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MARKING
DIAGRAMS
5
1
SOT鈭?53/SC70鈭?/SC鈭?8A
DF SUFFIX
CASE 419A
d = Date Code
5
5
L1 D
5
1
SOT鈭?53
XV5 SUFFIX
CASE 463B
L1
D
4
Y
1
1
5
L1
d
Tiny SOT鈭?53 and SOT鈭?53 Packages
2.7 ns T
PD
at 5 V (typ)
Source/Sink 24 mA at 3.0 V
Over鈭扸
oltage Tolerant Inputs
Pin For Pin with NC7SZ00P5X, TC7SZ00FU and TC7SZ00AFE
Chip Complexity: FETs = 20
Designed for 1.65 V to 5.5 V V
CC
Operation
Pb鈭扚ree Packages are Available
B
1
V
CC
A
2
= Device Marking
= One Digit Date Code
GND
3
PIN ASSIGNMENT
Pin
1
Function
A
B
GND
Y
V
CC
Figure 1. Pinout
(Top View)
2
3
A
B
4
&
Y
5
Figure 2. Logic Symbol
FUNCTION TABLE
Output
Input
A
L
L
H
H
B
L
H
L
H
Y = AB
Y
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2005
1
January, 2005 鈭?Rev. 4
Publication Order Number:
NL17SZ00/D