NJ88C22
Frequency Synthesiser with resettable counters
DS2439 - 2.2
The NJ88C22 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable 鈥楳鈥?counter,
7-bit programmable 鈥楢鈥?counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviated to 17 bits, when only the 鈥楢鈥?and 鈥楳鈥?counters require
changing.
The NJ88C22 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8715 series to produce a
universal binary coded synthesiser for up to 1100MHz operation.
PDA
PDB
LD
FIN
V
SS
V
DD
OSC IN
OSC OUT
1
2
3
4
16
15
14
13
CH
RB
MC
PDA
PDB
NC
ENABLE
LD
F
IN
CLOCK
V
SS
DATA
V
DD
NC
NC
OSC IN
CAP
1
2
3
4
5
6
7
8
9
18
17
16
15
NJ88C22
14
13
12
11
10
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
NC
OSC OUT
NJ88C22
5
6
7
8
12
11
10
9
DG16, DP16
FEATURES
s
Low Power Consumption
MP18
Fig.1 Pin connections - top view (not to scale)
s
s
s
s
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
>20MHz Input Frequency
Fast Lock-up Time
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
2V
SS
:
Input voltage
Open drain output, LD pin:
All other pins:
Storage temperature:
20路75V
to 7V
7V
V
SS
20路3V
to V
DD
10路3V
255擄C
to
1125擄C
(DP and MP packages)
265擄C
to
1150擄C
(DG package)
CAP
17
(15)
CH
16
(18)
ORDERING INFORMATION
NJ88C22 MA DG
Ceramic DIL Package
NJ88C22 MA DP
Plastic DIL Package
NJ88C22 MA MP
Miniature Plastic DIL Package
RB
15
(17)
OSC IN
OSC OUT
7 (9)
8 (10)
LATCH 6 LATCH 7 LATCH 8
10 (12)
DATA 12 (14)
ENABLE
11 (13)
REFERENCE COUNTER
(11BITS)
42
梅
f
r
SAMPLE/HOLD 1 (1)
PDA
PHASE
DETECTOR
鈥楻鈥?REGISTER
f
V
FREQUENCY/
PHASE
DETECTOR
2 (2)
PDB
CLOCK
鈥楳鈥?REGISTER
鈥楢鈥?REGISTER
3 (4)
LOCK DETECT (LD)
V
SS
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
F
IN
4 (5)
鈥楳鈥?COUNTER
(10 BITS)
鈥楢鈥?COUNTER
(7 BITS)
V
DD
V
SS
6 (7)
CONTROL LOGIC
5 (6)
14 (16) MODULUS
CONTROL
OUTPUT (MC)
Fig.2 Block diagram (MP pinout shown in parentheses)
ZARLINK
1
2
3
4
5
6
7
