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NIMD6302R2 Datasheet

  • NIMD6302R2

  • HDPlus Dual N-Channe Self-protected Field Effect Transistors...

  • 12頁

  • ONSEMI

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NIMD6302R2
HDPlus Dual N-Channel
Self-protected Field Effect
Transistors with 1:200
Current Mirror FET
HDPlus devices are an advanced HDTMOS鈩?series of power
MOSFET which utilize ON鈥檚 latest MOSFET technology process to
achieve the lowest possible on鈥搑esistance per silicon area while
incorporating smart features. They are capable of withstanding high
energy in the avalanche and commutation modes. The avalanche
energy is specified to eliminate guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
This HDPlus device features an integrated Gate鈥搕o鈥揝ource clamp
for ESD protection. Also, this device features a mirror FET for current
monitoring.
鈥?/div>
鹵3.5%
Current Mirror Accuracy in Linear Region
鈥?/div>
鹵15%
Current Mirror Accuracy in Low Current Saturation Region
鈥?/div>
IDSS Specified at Elevated Temperature
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Current Sense FET
鈥?/div>
ESD Protected on the Main and the Mirror FET
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated in this specification is not
implied. Exposure to absolute maximum rated conditions for extended peri-
ods may affect device reliability.
http://onsemi.com
5.0 AMPERES
30 VOLTS
R
DS(on)
= 50 mW
ISOLATED DUAL PACKAGING
Drain1
Drain2
Gate1
Mirror
Main
FET
Gate2
Mirror
Main
FET
Mirror1
Source1
Mirror2
Source2
SOIC鈥?
CASE 751
STYLE 19
MAIN MOSFET MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Drain鈥搕o鈥揋ate Voltage (R
GS
= 1.0 MW)
Gate鈥搕o鈥揝ource Voltage
Drain Current
鈥?Continuous @ T
A
= 25擄C
鈥?Continuous @ T
A
= 100擄C (Note 3)
鈥?Pulsed (t
p
v10
ms)
Total Power Dissipation @ T
A
= 25擄C (Note 1)
Total Power Dissipation @ T
A
= 25擄C (Note 2)
Thermal Resistance
Junction鈥搕o鈥揂mbient (Note 1)
Junction鈥搕o鈥揂mbient (Note 2)
Single Pulse Drain鈥搕o鈥揝ource Avalanche
Energy (Note 3)
(V
DD
= 25 Vdc, V
GS
= 10 Vdc,
V
DS
= 20 Vdc, I
L
= 15 Apk, L = 10 mH, R
G
=
25
W)
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
P
D
R
qJA
R
qJA
E
AS
Value
30
30
"16
6.5
4.4
33
1.3
1.67
96
75
250
mJ
Unit
Vdc
Vdc
Vdc
Adc
Adc
Apk
W
擄C/W
MARKING DIAGRAM
Source 1
Gate 1
Source 2
Gate 2
1
2
3
4
(Top View)
N6302
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
N6302
AYWW
8
7
6
5
Mirror 1
Drain 1
Mirror 2
Drain 2
ORDERING INFORMATION
Device
NIMD6302R2
Package
SOIC鈥?
Shipping
2500/Tape & Reel
1. Mounted onto min pad board.
2. Mounted onto 1鈥?pad board.
3. Switching characteristics are independent of operating junction tempera-
tures.
漏
Semiconductor Components Industries, LLC, 2002
1
October, 2002 鈥?Rev. 3
Publication Order Number:
NIMD6302R2/D

NIMD6302R2 產(chǎn)品屬性

  • ON Semiconductor

  • MOSFET

  • N-Channel

  • 30 V

  • +/- 16 V

  • 6.5 A

  • 0.05 Ohms

  • Dual

  • SMD/SMT

  • SOIC-8

  • Reel

  • 56.5 ns, 2.7 ns

  • 19.8 S

  • 1.3 W

  • 56.5 ns, 2.7 ns

  • 2500

  • 35.9 ns, 66.5 ns

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