鈥?/div>
Ideal for Coil鈭抩n鈭扨lug Applications
DPAK Package Offers Smaller Footprint for Increased Board Space
Gate鈭扙mitter ESD Protection
Temperature Compensated Gate鈭扖ollector Voltage Clamp Limits
Stress Applied to Load
Integrated ESD Diode Protection
New Design Increases Unclamped Inductive Switching (UIS) Energy
Per Area
Low Threshold Voltage Interfaces Power Loads to Logic or
Microprocessor Devices
Low Saturation Voltage
High Pulsed Current Capability
Optional Gate Resistor (R
G
) and Gate鈭扙mitter Resistor (R
GE
)
Emitter Ballasting for Short鈭扖ircuit Capability
18 AMPS
400 VOLTS
V
CE(on)
3
2.0 V @
I
C
= 10 A, V
GE
.
4.5 V
C
G
RG
RGE
E
4
1 2
3
DPAK
CASE 369C
STYLE 7
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Collector鈭扙mitter Voltage
Collector鈭扜ate Voltage
Gate鈭扙mitter Voltage
Collector Current鈭扖ontinuous
@ T
C
= 25擄C 鈭?Pulsed
ESD (Human Body Model)
R = 1500
鈩?
C = 100 pF
ESD (Machine Model) R = 0
鈩?
C = 200 pF
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
Operating and Storage Temperature Range
Symbol
V
CES
V
CER
V
GE
I
C
ESD
8.0
ESD
P
D
T
J
, T
stg
800
115
0.77
鈭?5 to
+175
V
Watts
W/擄C
擄C
G18N40B = NGD18N40CLB
Y
= Year
WW
= Work Week
Value
430
430
18
15
50
Unit
V
DC
V
DC
V
DC
A
DC
A
AC
kV
1
Gate
2
Collector
3
Emitter
YWW
G18
N40B
4
Collector
MARKING
DIAGRAM
ORDERING INFORMATION
Device
NGD18N40CLB
NGD18N40CLBT4
Package
DPAK
DPAK
Shipping
鈥?/div>
75 Units/Rail
2500/Tape & Reel
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
漏
Semiconductor Components Industries, LLC, 2003
1
November, 2003 鈭?Rev. 5
Publication Order Number:
NGD18N40CLB/D
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