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NG80960JD-40 Datasheet

  • NG80960JD-40

  • 3.3 V EMBEDDED 32-BIT MICROPROCESSOR

  • 736.76KB

  • 59頁

  • INTEL   INTEL

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PRODUCT PREVIEW
80960JD
3.3 V EMBEDDED 32-BIT MICROPROCESSOR
鈥?3.3 V, 5 V Tolerant, Version of the 80960JD Processor
s
Pin/Code Compatible with all 80960Jx
s
3.3 V Supply Voltage
Processors
s
High-Performance Embedded Architecture
s
s
s
s
鈥?One Instruction/Clock Execution
鈥?Core Clock Rate is 2x the Bus Clock
鈥?Load/Store Programming Model
鈥?Sixteen 32-Bit Global Registers
鈥?Sixteen 32-Bit Local Registers (8 sets)
鈥?Nine Addressing Modes
鈥?User/Supervisor Protection Model
Two-Way Set Associative Instruction Cache
鈥?80960JD - 4 Kbyte
鈥?Programmable Cache Locking
Mechanism
Direct Mapped Data Cache
鈥?80960JD - 2 Kbyte
鈥?Write Through Operation
On-Chip Stack Frame Cache
鈥?Seven Register Sets Can Be Saved
鈥?Automatic Allocation on Call/Return
鈥?0-7 Frames Reserved for High-Priority
Interrupts
On-Chip Data RAM
鈥?1 Kbyte Critical Variable Storage
鈥?Single-Cycle Access
s
s
s
s
鈥?5 V Tolerant Inputs
鈥?TTL Compatible Outputs
High Bandwidth Burst Bus
鈥?32-Bit Multiplexed Address/Data
鈥?Programmable Memory Configuration
鈥?Selectable 8-, 16-, 32-Bit Bus Widths
鈥?Supports Unaligned Accesses
鈥?Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
鈥?31 Programmable Priorities
鈥?Eight Maskable Pins plus NMI
鈥?Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
鈥?Independent 32-Bit Counting
鈥?Clock Prescaling by 1, 2, 4 or 8
鈥?lnternal Interrupt Sources
Halt Mode for Low Power
Compatibility
s
IEEE 1149.1 (JTAG) Boundary Scan
s
Packages
鈥?132-Lead Pin Grid Array (PGA)
鈥?132-Lead Plastic Quad Flat Pack (PQFP)
132
PIN 1
99
i
A80960JD
XXXXXXXXC0
M
漏 19xx
i960
廬
i
33
NG80960JD
XXXXXXXXC0S
M
漏 19xx
66
Figure 1.
80960JD Microprocessor
漏 INTEL CORPORATION, 1996
November 1996
Order Number:
272971-001

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