Freescale Semiconductor, Inc.
Fa c t S h e e t
NETRAMFACT/D
Rev. 8
Motor ola NetRAMs
Networking Dual-Por ted Memor y for the Communications Market
Motorola鈥檚 NetRAM devices are designed to meet an optimal price and performance point for dual-port appli-
cations. These devices enable data to flow quickly so Local Area Network (LAN) and Wide Area Network
(WAN) devices can devote more of their resources to application performance
Product Description
The NetRAM family is offered in 1, 4, and 8 Mb densities. The NetRAM allows the user to concurrently per-
form reads or writes in combination on the two data ports. The two address ports determine the read or write
locations for their respective data ports.
The synchronous design allows for precise control with the use of a single external clock. Chip enables,
addresses, input data, and write enables for each port are registered on the rising edge of the clock. The output
enable for each port is asynchronous in nature.
For the case when the addresses for each port are the same, certain protocols are followed. If both ports are
read, the reads occur normally. If one port is writing and the other is being read, the read from the array will
occur before the new data is written. If both ports are writing, only the data from Port-Y will be written to the
array.
Functional additions have been made to successive generations of the NetRAM to allow the user more flexibili-
ty in design. The 4 Mb device offers two chip enables for each port over the single pair of chip enables for
each 1 Mb device. The 8 Mb NetRAM adds a third chip enable per port and byte write capability.
Freescale Semiconductor, Inc...
Product Highlights
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Single Clock Operation
Self-Timed Write
Pipelined Read Operation
Two Bi-Directional Data Buses
Asynchronous Output Enables
Applications
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ATM
Routers
Cell / Frame Buffers
RAID Systems
Ethernet Switches
Cellular Base Stations
SNA Switches
NetRAM Family Summary
Density
Configuration
PowerSupply
Write Operation
Read Operation
Deselect
Port-to-Port Pass Through
Byte Write Capability
Operating Frequency
Package
1 Mb
32K x 36 and 64K x 18
3.3V
鹵
5%
4 Mb
128K x 36
3.3V
鹵
5%
8 Mb
256K x 36
3.3V
鹵
5% and
2.5V
鹵
200mV
Self-Timed Early Write Self-Timed Early Write Self-Timed Early Write
Pipelined
Dual Cycle
Yes
No
66, 83, 100 MHz
176 TQFP
(100 TQFP for x 18)
Pipelined
Dual Cycle
Yes
No
100, 133 MHz
176 TQFP
Pipelined
Dual Cycle
No
Yes
100 MHz
209 MAPBGA
For More Information On This Product,
Go to: www.freescale.com
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