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NE33200N Datasheet

  • NE33200N

  • SUPER LOW NOISE HJ FET

  • 7頁(yè)

  • NEC   NEC

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SUPER LOW NOISE HJ FET
NE33200
FEATURES
鈥?VERY LOW NOISE FIGURE:
0.75 dB typical at 12 GHz
Optimum Noise Figure, NF
OPT
(dB)
4
3.5
NOISE FIGURE & ASSOCIATED
GAIN vs. FREQUENCY
V
DS
= 2 V, I
DS
= 10 mA
24
21
18
15
12
9
6
NF
0.5
0
1
10
30
3
0
鈥?HIGH ASSOCIATED GAIN:
10.5 dB Typical at 12 GHz
鈥?GATE LENGTH:
0.3
碌m
鈥?GATE WIDTH:
280
碌m
3
2.5
2
1.5
1
DESCRIPTION
The NE33200 is a Hetero-Junction FET chip that utilizes the
junction between Si-doped AlGaAs and undoped InGaAs to
create a two-dimensional electron gas layer with very high
electron mobility. Its excellent low noise figure and high
associated gain make it suitable for commercial and industrial
applications.
NEC's stringent quality assurance and test procedures as-
sure the highest reliability and performance.
Frequency, f (GHz)
ELECTRICAL CHARACTERISTICS
(T
A
= 25擄C)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
NF
OPT
1
PARAMETERS AND CONDITIONS
Noise Figure, V
DS
= 2 V, I
D
= 10 mA,
f = 4 GHz
f = 12 GHz
Associated Gain, V
DS
= 2 V, I
D
= 10 mA,
f = 4 GHz
f = 12 GHz
Output Power at 1 dB Gain Compression Point, f = 12 GHz
V
DS
= 2 V, I
DS
= 10 mA
V
DS
= 2 V, I
DS
= 20 mA
Gain at P
1dB
, f = 12 GHz
V
DS
= 2 V, I
DS
= 10 mA
V
DS
= 2 V, I
DS
= 20 mA
Saturated Drain Current, V
DS
= 2 V, V
GS
= 0 V
Pinch-off Voltage, V
DS
= 2 V, I
D
= 100
碌A(chǔ)
Transconductance, V
DS
= 2 V, I
D
= 10 mA
Gate to Source Leakage Current, V
GS
= -5 V
Thermal Resistance (Channel to Case)
UNITS
dB
dB
dB
dB
dBm
dBm
dB
dB
mA
V
mS
碌A(chǔ)
擄C/W
15
-2.0
45
MIN
NE33200
00 (Chip)
TYP
0.35
0.75
15.0
10.5
11.2
12.0
11.8
12.8
40
-0.8
70
0.5
10
240
80
-0.2
MAX
1.0
G
A
1
9.5
P
1dB
G
1dB
I
DSS
V
P
g
m
I
GSO
R
TH(CH-C)2
Notes:
1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects for
10 samples.
2. Chip mounted on infinite heat sink.
California Eastern Laboratories
Associated Gain, G
A
(dB)
Ga

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