DATA SHEET
HETERO JUNCTION FIELD EFFECT TRANSISTOR
NE32500, NE27200
C to Ka BAND SUPER LOW NOISE AMPLIFIER
N-CHANNEL HJ-FET CHIP
DESCRIPTION
NE32500 and NE27200 are Hetero Junction FET chip that utilizes the hetero junction between Si-doped AlGaAs
and undoped InGaAs to create high mobility electrons. Its excellent low noise and high associated gain make it suitable
for commercial systems, industrial and space applications.
FEATURES
鈥?Super Low Noise Figure & High Associated Gain
NF = 0.45 dB TYP., G
a
= 12.5 dB TYP. at f = 12 GHz
鈥?Gate Length : L
g
= 0.2
碌
m
鈥?Gate Width : W
g
= 200
碌
m
ORDERING INFORMATION
PART NUMBER
NE32500
NE27200
Standard (Grade D)
Special, specific (Grade C and B)
QUALITY GRADE
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 藲C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Total Power Dissipation
Channel Temperature
Storage Temperature
V
DS
V
GS
I
D
P
tot
*
T
ch
T
stg
4.0
鈥?.0
I
DSS
200
175
鈥?5 to +175
V
V
mA
mW
擄C
擄C
*
Chip mounted on a Alumina heatsink (size: 3
脳
3
脳
0.6
t
)
ELECTRICAL CHARACTERISTICS (T
A
= 25 藲C)
PARAMETER
Gate to Source Leak Current
Saturated Drain Current
Gate to Source Cutoff Voltage
Transconductance
Thermal Resistance
Noise Figure
Associated Gain
SYMBOL
I
GSO
I
DSS
V
GS(off)
g
m
R
th
*
NF
G
a
MIN.
鈥?/div>
20
鈥?.2
45
鈥?/div>
鈥?/div>
11.0
TYP.
0.5
60
鈥?.7
60
鈥?/div>
0.45
12.5
MAX.
10
90
鈥?.0
鈥?/div>
260
0.55
鈥?/div>
UNIT
TEST CONDITIONS
V
GS
= 鈥? V
V
DS
= 2 V, V
GS
= 0 V
V
DS
= 2 V, I
D
= 100
碌
A
V
DS
= 2 V, I
D
= 10 mA
channel to case
V
DS
= 2 V, I
D
= 10 mA, f = 12 GHz
碌
A
mA
V
mS
藲C/W
dB
dB
RF performance is determined by packaging and testing 10 chips per wafer.
Wafer rejection criteria for standard devices is 2 rejects per 10 samples.
Document No. P11512EJ2V0DS00 (2nd edition)
Date Published January 1997 N
Printed in Japan
漏
1996
NE32500相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
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