NEC's C TO KA BAND
SUPER LOW NOISE AMPLIFIER
N-CHANNEL HJ FET CHIP
FEATURES
鈥?SUPER LOW NOISE FIGURE:
0.45 dB TYP at 12 GHz
鈥?HIGH ASSOCIATED GAIN:
12.5 dB TYP at 12 GHz
碌m
鈥?GATE LENGTH: L
G
= 0.20
碌
鈥?GATE WIDTH: W
G
= 200
碌
m
89
25
13
Drain
NE32500
OUTLINE DIMENSIONS
(Units in
碌m)
CHIP
58
5.5
36.5
13
66
25
38
68
DESCRIPTION
NEC's NE32500 is a Hetero-Junction FET chip that uses the
junction between Si-doped AlGaAs and undoped InGaAs to
create very high mobility electrons. Its excellent low noise figure
and high associated gain make it suitable for commercial
systems and industrial applications.
NEC's stringent quality assurance and test procedures assure
the highest reliability and performance.
350
76.5
Source
Source
100.5
Gate
21
25
25
13
66
49.5
43
350
60
46.5
Thickness = 140
碌m
Bonding Area
ELECTRICAL CHARACTERISTICS
(T
A
= 25擄C)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
NF
G
A
I
DSS
g
m
I
GSO
V
GS
(off)
R
TH (CH-C)
PARAMETERS AND CONDITIONS
Noise Figure, V
DS
= 2 V, I
DS
= 10 mA, f = 12 GHz
Associated Gain, V
DS
= 2 V, I
DS
= 10 mA, f = 12 GHz
Saturated Drain Current, V
DS
= 2 V,V
GS
= 0 V
Transconductance, V
DS
= 2 V, I
D
= 10 mA
Gate to Source Leakage Current, V
GS
= -3 V
Gate to Source Cutoff Voltage, VDS = 2 V, ID = 100
碌A(chǔ)
Thermal Resistance
1
(Channel to Case)
UNITS
dB
dB
mA
mS
碌A(chǔ)
V
擄C/W
-0.2
11.0
20
45
MIN
NE32500
00 (Chip)
TYP
0.45
12.5
60
60
0.5
-0.7
10.0
-2.0
260
90
MAX
0.55
Note:
1. RF performance is determined by packaging and testing 10 chips per wafer.
Wafer rejection criteria for standard devices is 2 rejects per 10 samples.
California Eastern Laboratories
CEL
1
2
3
