August 1996
NDT410EL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Power SOT N-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance, provide superior
switching performance, and withstand high energy pulses
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
2.1A 100V. R
DS(ON)
= 0.25
鈩?/div>
@ V
GS
= 5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
___________________________________________________________________________________________
D
D
G
D
S
G
S
ABSOLUTE MAXIMUM RATINGS
T
A
= 25擄C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
NDT410EL
100
20
2.1
10
3
1.3
1.1
-65 to 150
Units
V
V
A
W
T
J
,T
STG
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
R
胃
JA
R
胃
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
擄C/W
擄C/W
* Order option J23Z for cropped center drain lead.
漏 1997 Fairchild Semiconductor Corporation
NDT410EL Rev. B1
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