August 1998
NDT3055L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance and provide superior
switching performance, and withstand high energy pulse
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to
transients are needed.
Features
4 A, 60 V. R
DS(ON)
= 0.100
鈩?/div>
@ V
GS
= 10 V,
R
DS(ON)
= 0.120
鈩?/div>
@ V
GS
= 4.5 V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
SuperSOT
TM
-3
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D
D
D
D
S
D
SOT-223
S
G
D
S
G
SOT-223
*
(J23Z)
G
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
T
A
= 25
o
C unless otherwise noted
NDT3055L
60
鹵20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
4
25
3
1.3
1.1
-65 to 150
W
T
J
,T
STG
R
胃
JA
R
胃
JC
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
擄C/W
擄C/W
* Order option J23Z for cropped center drain lead.
漏 1998 Fairchild Semiconductor Corporation
NDT3055L Rev.A1
1
2
3
4
5
