February 1996
NDS9405
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
been especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
-4.3A, -20V. R
DS(ON)
= 0.10
鈩?/div>
@ V
GS
= -10V
High density cell design for extremely low R
DS(ON)
High power and current handling capability in a widely used
surface mount package.
____________________________________________________________________________________
5
6
4
3
7
8
2
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
T
A
= 25擄C unless otherwise noted
NDS9405
-20
鹵 20
(Note 1a)
(Note 1a)
Units
V
V
A
Drain Current - Continuous T
A
= 25擄C
- Continuous T
A
= 70擄C
- Pulsed
T
A
= 25擄C
鹵 4.3
鹵 3.3
鹵 20
P
D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
2.5
W
1.2
1
-55 to 150
擄C
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
胃
JA
R
胃
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
擄C/W
擄C/W
NDS9405.SAM
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