June 1996
NDS8433
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
-5.2A, -20V. R
DS(ON)
= 0.055
鈩?/div>
@ V
GS
= -4.5V
R
DS(ON)
= 0.075
鈩?/div>
@ V
GS
= -2.7V.
High density cell design for extremely low R
DS(ON).
High power and current handling capability in a widely used
surface mount package.
____________________________________________________________________________________________
5
6
7
4
3
2
1
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
A
= 25擄C unless otherwise noted
NDS8433
-20
-8
(Note 1a)
Units
V
V
A
-5.2
-20
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
2.5
1.2
1
-55 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
R
胃
JA
R
胃
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
擄C/W
擄C/W
漏 1997 Fairchild Semiconductor Corporation
NDS8433 Rev. B1
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