NDS356 Datasheet

IC型號(hào)：
NDS356
PDF描述：
P-Channel Logic Level Enhancement Mode Field Effect Transist...
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芯片廠家：
FAIRCHILD

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September 1996

NDS356AP

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

SuperSOT

-3

P-Channel logic level enhancement mode

power field effect transistors are produced using Fairchild's

proprietary, high cell density, DMOS technology. This very high

density process is especially tailored to minimize on-state

resistance. These devices are particularly suited for low voltage

applications such as notebook computer power management,

portable electronics, and other battery powered circuits where

fast high-side switching, and low in-line power loss

are

needed in a very small outline surface mount package.

Features

-1.1 A, -30 V, R

DS(ON)

= 0.3

鈩?/div>

@ V

=-4.5 V

DS(ON)

= 0.2

鈩?/div>

@ V

=-10 V.

Industry standard outline SOT-23 surface mount package

using proprietary SuperSOT

-3 design for superior

thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

Exceptional on-resistance and maximum DC current

capability.

________________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

GSS

STG

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDS356AP

-30

鹵20

(Note 1a)

Units

Gate-Source Voltage - Continuous

Maximum Drain Current - Continuous

- Pulsed

Maximum Power Dissipation

(Note 1a)

(Note 1b)

鹵1.1

鹵10

0.5

0.46

-55 to 150

Operating and Storage Temperature Range

擄C

THERMAL CHARACTERISTICS

胃

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

(Note 1a)

(Note 1)

250

擄C/W

漏 1997 Fairchild Semiconductor Corporation

NDS356AP Rev.C

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