March 1996
NDS351N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMCIA cards, and other
battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline
surface mount package.
Features
1.1A, 30V. R
DS(ON)
= 0.25
鈩?/div>
@ V
GS
= 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25擄C unless otherwise noted
NDS351N
30
20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
鹵 1.1
鹵 10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
擄C
THERMAL CHARACTERISTICS
R
胃
JA
R
胃
JC
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
(Note 1)
擄C/W
擄C/W
Thermal Resistance, Junction-to-Case
75
漏 1997 Fairchild Semiconductor Corporation
NDS351N Rev. E2
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