NDS335 Datasheet

IC型號：
NDS335
PDF描述：
N-Channel Logic Level Enhancement Mode Field Effect Transist...
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PDF頁數(shù)：
6頁
芯片廠家：
FAIRCHILD

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July 1996

NDS335N

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These N -Channel logic level enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage

applications in notebook computers, portable phones, PCMCIA

cards, and other battery powered circuits where fast switching,

and low in-line power loss are needed in a very small outline

surface mount package.

Features

1.7 A, 20 V. R

DS(ON)

= 0.14

鈩?/div>

@ V

= 2.7 V

DS(ON)

= 0.11

鈩?/div>

@ V

= 4.5 V.

Industry standard outline SOT-23 surface mount package

using poprietary SuperSOT

-3 design for superior thermal

and electrical capabilities.

High density cell design for extremely low R

DS(ON)

Exceptional on-resistance and maximum DC current

capability.

________________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

GSS

STG

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDS335N

1.7

(Note 1a)

(Note 1b)

Units

Gate-Source Voltage - Continuous

Maximum Drain Current - Continuous

(Note 1a)

- Pulsed

Maximum Power Dissipation

0.5

0.46

-55 to 150

Operating and Storage Temperature Range

擄C

THERMAL CHARACTERISTICS

胃

Thermal Resistance, Junction-to-Ambient

(Note 1a)

250

擄C/W

Thermal Resistance, Junction-to-Case

(Note 1)

漏 1997 Fairchild Semiconductor Corporation

NDS335 Rev.C

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