NDP7052 Datasheet

IC型號(hào)：
NDP7052
PDF描述：
N-Channel Enhancement Mode Field Effect Transistor
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60.64KB
PDF頁(yè)數(shù)：
6頁(yè)
芯片廠家：
FAIRCHILD

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June 1997

NDP7052 / NDB7052

N-Channel Enhancement Mode Field Effect Transistor

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process has

been especially tailored to minimize on-state resistance,

provide superior switching performance, and withstand high

energy pulses in the avalanche and commutation modes.

These devices are particularly suited for low voltage

applications such as automotive, DC/DC converters, PWM

motor controls, and other battery powered circuits where fast

switching, low in-line power loss, and resistance to transients

are needed.

Features

75 A, 50 V. R

DS(ON)

= 0.01

鈩?/div>

@ V

= 10 V.

Critical DC electrical parameters specified at elevated

temperature.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175擄C maximum junction temperature rating.

High density cell design for extremely low R

DS(ON)

TO-220 and TO-263 (D

PAK) package for both through hole

and surface mount applications.

________________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

DGR

GSS

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDP7052

鹵20

鹵40

225

150

-65 to 175

NDB7052

Units

Drain-Gate Voltage (R

< 1 M

鈩?/div>

)

Gate-Source Voltage - Continuous

- Nonrepetitive (t

< 50 碌s)

Drain Current

- Continuous

- Pulsed

Total Power Dissipation @ T

= 25擄C

Derate above 25擄C

W/擄C

擄C

STG

胃JC

胃

Operating and Storage Temperature Range

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

62.5

擄C/W

漏 1997 Fairchild Semiconductor Corporation

NDP7052 Rev.B1

型號(hào)

版本

描述

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