April 1996
NDP6050L / NDB6050L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
48A, 50V. R
DS(ON)
= 0.025
鈩?/div>
@ V
GS
= 5V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175擄C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25擄C unless otherwise noted
NDP6050L
50
50
鹵 16
鹵 25
48
144
100
0.67
-65 to 175
275
NDB6050L
Units
V
V
V
Drain-Gate Voltage (R
GS
< 1 M
鈩?/div>
)
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 碌s)
Drain Current
- Continuous
- Pulsed
A
P
D
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
W
W/擄C
擄C
擄C
T
J
,T
STG
T
L
Operating and Storage Temperature
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
漏 1997 Fairchild Semiconductor Corporation
NDP6050L Rev. C / NDB6050L Rev. D
1
2
3
4
5
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