January 1996
NDP603AL / NDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance.
These devices are
particularly suited for low voltage applications such as
DC/DC converters and high efficiency switching circuits
where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
25A, 30V. R
DS(ON)
= 0.022
鈩?/div>
@ V
GS
=10V
.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R
DS(ON)
.
175擄C maximum junction temperature rating.
______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25擄C unless otherwise noted
NDP603AL
30
鹵 20
25
(Note 1)
NDB603AL
Units
V
V
A
Gate-Source Voltage - Continuous
Drain Current
- Continuous
- Pulsed
100
50
0.4
-65 to 175
275
W
W/擄C
擄C
擄C
P
D
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
T
J
,T
STG
T
L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
THERMAL CHARACTERISTICS
R
胃
JC
R
胃
JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
2.5
62.5
擄C/W
擄C/W
漏 1997 Fairchild Semiconductor Corporation
NDP603AL.SAM
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