October 1996
NDP5060L / NDB5060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored
to minimize on-state resistance, provide superior
switching performance, and withstand high energy
pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as automotive, DC/DC converters,
PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
Features
26 A, 60 V. R
DS(ON)
= 0.05
鈩?/div>
@ V
GS
= 5 V
R
DS(ON)
= 0.035
鈩?/div>
@ V
GS
= 10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175擄C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25擄C unless otherwise noted
NDP5060L
60
60
鹵16
鹵25
26
78
68
0.45
-65 to 175
NDB5060L
Units
V
V
V
Drain-Gate Voltage (R
GS
< 1 M
鈩?/div>
)
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 碌s)
Drain Current
- Continuous
- Pulsed
A
P
D
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
W
W/擄C
擄C
T
J
,T
STG
Operating and Storage Temperature Range
漏 1997 Fairchild Semiconductor Corporation
NDP5060L Rev.A
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