July 1996
NDP4060 / NDB4060
N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process has
been especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
Features
15A, 60V. R
DS(ON)
= 0.10
鈩?/div>
@ V
GS
=10V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175擄C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
___________________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
Drain-Gate Voltage (R
GS
< 1 M
鈩?/div>
)
T
C
= 25擄C unles otherwise noted
NDP4060
60
60
鹵 20
鹵 40
鹵 15
鹵 45
50
0.33
-65 to 175
275
NDB4060
Units
V
V
V
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 碌s)
Drain Current - Continuous
- Pulsed
A
P
D
T
J
,T
STG
T
L
Total Power Dissipation
Derate above 25擄C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
W
W/擄C
擄C
擄C
漏 1997 Fairchild Semiconductor Corporation
NDP4060 Rev. C
1
2
3
4
5
6
