NDB7051L Datasheet

IC型號：
NDB7051L
PDF描述：
N-Channel Logic Level Enhancement Mode Field Effect Transist...
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360.74KB
PDF頁數(shù)：
12頁
芯片廠家：
FAIRCHILD

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September 1996

NDP7051L / NDB7051L

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These logic level N-Channel enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process has been especially tailored to minimize on-state

resistance, provide superior switching performance, and

withstand high energy pulses in the avalanche and

commutation modes. These devices are particularly suited for

low voltage applications such as automotive, DC/DC

converters, PWM motor controls, and other battery powered

circuits where fast switching, low in-line power loss, and

resistance to transients are needed.

Features

67 A, 50 V. R

DS(ON)

= 0.0145

鈩?/div>

@ V

= 5 V

DS(ON)

= 0.0115

鈩?/div>

@ V

= 10 V.

Low drive requirements allowing operation directly from logic

drivers. V

GS(TH)

< 2.0V.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175擄C maximum junction temperature rating.

High density cell design for extremely low R

DS(ON)

TO-220 and TO-263 (D

PAK) package for both through hole

and surface mount applications.

________________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

DGR

GSS

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDP7051L

鹵16

鹵25

200

130

0.87

-65 to 175

NDB7051L

Units

Drain-Gate Voltage (R

< 1 M

鈩?/div>

)

Gate-Source Voltage - Continuous

- Nonrepetitive (t

< 50 碌s)

Drain Current

- Continuous

- Pulsed

Maximum Power Dissipation @ T

= 25擄C

Derate above 25擄C

W/擄C

擄C

STG

Operating and Storage Temperature Range

漏 1997 Fairchild Semiconductor Corporation

NDP7051L Rev.D/NDB7051L Rev.E

型號

版本

描述

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