July 1997
NDP6030 / NDB6030
N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process has
been especially tailored to minimize on-state resistance and
provide superior switching performance. These devices are
particularly suited for low voltage applications such as DC/DC
converters and other battery powered circuits where fast
switching, low in-line power loss, and resistance to transients
are needed.
Features
46 A, 30 V. R
DS(ON)
= 0.018 @ V
GS
=10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175擄C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25擄C unless otherwise noted
NDP6030
30
30
鹵20
46
135
75
0.5
-65 to 175
NDB6030
Units
V
V
V
A
Drain-Gate Voltage (R
GS
< 1 M
鈩?/div>
)
Gate-Source Voltage - Continuous
Drain Current
- Continuous
- Pulsed
P
D
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
W
W/擄C
擄C
T
J
,T
STG
R
胃JC
R
胃
JA
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
2
62.5
擄C/W
擄C/W
漏 1997 Fairchild Semiconductor Corporation
NDP6030.RevB
1
2
3
4
