November 1996
NDP6020 / NDB6020
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using National's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored
to minimize on-state resistance, provide superior
switching performance, and withstand high energy
pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as automotive, DC/DC converters,
PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
Features
35 A, 20 V. R
DS(ON)
= 0.023
鈩?/div>
@ V
GS
= 4.5 V
R
DS(ON)
= 0.028
鈩?/div>
@ V
GS
= 2.7 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175擄C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through
hole and surface mount applications.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
Parameter
T
C
= 25擄C unless otherwise noted
NDP6020
NDB6020
Units
V
DSS
V
DGR
V
GSS
I
D
Drain-Source Voltage
Drain-Gate Voltage (R
GS
< 1 M
鈩?/div>
)
Gate-Source Voltage - Continuous
Drain Current
- Continuous
- Pulsed
20
20
鹵8
35
100
60
0.4
-65 to 175
V
V
V
A
P
D
Total Power Dissipation @ T
C
= 25
擄
C
Derate above 25
擄
C
W
W/
擄
C
擄C
T
J
,T
STG
Operating and Storage Temperature Range
漏 1997 Fairchild Semiconductor Corporation
NDP6020 Rev.C
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