NDB4050L Datasheet

IC型號(hào)：
NDB4050L
PDF描述：
N-Channel Logic Level Enhancement Mode Field Effect Transist...
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PDF頁(yè)數(shù)：
6頁(yè)
芯片廠家：
FAIRCHILD

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April 1996

NDP4050L / NDB4050L

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These logic level N-Channel enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process has been especially tailored to minimize on-state

resistance, provide superior switching performance, and

withstand high energy pulses in the avalanche and

commutation modes. These devices are particularly suited for

low voltage applications such as automotive, DC/DC

converters, PWM motor controls, and other battery powered

circuits where fast switching, low in-line power loss, and

resistance to transients are needed.

Features

15A, 50V. R

DS(ON)

= 0.1

鈩?/div>

@ V

= 5V

Low drive requirements allowing operation directly from logic

drivers. V

GS(TH)

< 2.0V.

Critical DC electrical parameters specified at elevated

temperature.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175擄C maximum junction temperature rating.

High density cell design for extremely low R

DS(ON)

TO-220 and TO-263 (D

PAK) package for both through hole

and surface mount applications.

_______________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

DGR

GSS

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDP4050L

鹵 16

鹵 25

0.33

-65 to 175

275

NDB4050L

Units

Drain-Gate Voltage (R

< 1 M

鈩?/div>

)

Gate-Source Voltage - Continuous

- Nonrepetitive (t

< 50 碌s)

Drain Current

- Continuous

- Pulsed

Total Power Dissipation @ T

= 25擄C

Derate above 25擄C

W/擄C

擄C

STG

Operating and Storage Temperature

Maximum lead temperature for soldering

purposes, 1/8" from case for 5 seconds

漏 1997 Fairchild Semiconductor Corporation

NDP4050L Rev. B / NDB4050L Rev. C

標(biāo)準(zhǔn)包裝
800
類別
分離式半導(dǎo)體產(chǎn)品
家庭
FET - 單
系列
-
FET 型
MOSFET N 通道，金屬氧化物
FET 特點(diǎn)
邏輯電平門
漏極至源極電壓(Vdss)
50V
電流 - 連續(xù)漏極(Id) @ 25° C
15A
開態(tài)Rds（最大）@ Id, Vgs @ 25° C
80 毫歐 @ 15A，10V
Id 時(shí)的 Vgs(th)（最大）
2V @ 250µA
閘電荷(Qg) @ Vgs
17nC @ 5V
輸入電容 (Ciss) @ Vds
600pF @ 25V
功率 - 最大
50W
安裝類型
表面貼裝
封裝/外殼
TO-263-3，D²Pak（2 引線+接片），TO-263AB
供應(yīng)商設(shè)備封裝
D²PAK
包裝
帶卷 (TR)
其它名稱
NDB4050LTR

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