鈥?/div>
Outputs
Programmable Power Sharing and Budgeting from Two Independent
Supplies
0.8 Volt
"1%
Reference for Low Voltage Outputs
1.5 A Peak Power Drive
Switch Blanking for Noise Sensitive Applications through use of
R
OSC
Pin
Programmable Frequency, 150 kHz to 750 kHz Operation
Programmable Soft Start
Cycle鈭抌y鈭扖ycle Overcurrent Protection
Independent Programmable Current Limits
100% Duty Cycle for Fast Transient Response
Internal Slope Compensation
Out鈭抩f鈭扨hase Synchronization between the Controllers
Input Undervoltage Lockout
On/Off Enable through use of the COMP Pins
Power Supply Sequencing
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATEH1
GATEL1
GND
BST
NC
NC
IS+1
IS鈭?
V
FB1
COMP1
A
WL
Y
WW
20
GATEH2
GATEL2
V
CC
R
OSC
MODE
IS鈭?
IS+2
V
REF2
V
FB2
COMP2
NCP
5425
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
NCP5425DB
NCP5425DBR2
Package
TSSOP鈭?0
TSSOP鈭?0
Shipping
鈥?/div>
61 Units/Rail
2500 Units/Reel
Applications
鈥?/div>
DDR Memory Power
鈥?/div>
Graphics Cards
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
漏
Semiconductor Components Industries, LLC, 2005
1
January, 2005 鈭?Rev. 6
Publication Order Number:
NCP5425/D
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