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NCP5210/D Datasheet

  • NCP5210/D

  • 3-In-1 PWM Dual Buck and Linear DDR Power Controller

  • 12頁

  • ETC

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NCP5210
Product Preview
3鈭捍n鈭? PWM Dual Buck and
Linear DDR Power
Controller
The NCP5210, 3鈭捍n鈭? PWM Dual Buck and Linear DDR Power
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the V
TT
termination voltage.
This IC contains two synchronous PWM buck controller for driving
four external NFETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of the reference voltage
with sourcing and sinking current.
Protective features include, soft鈭抯tart circuitry, under鈭抳oltage
monitoring of 5VDUAL, and BOOT voltage, and thermal shutdown.
The IC is packaged in a QFN鈭?0.
Features
http://onsemi.com
MARKING
DIAGRAM
NCP5210
AWLYYWW
1
20
1
20鈭扡EAD QFN
MN SUFFIX
CASE 505AB
鈥?/div>
Incorporates Synchronous PWM Buck Controllers for VDDQ and
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VMCH
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are N鈭抍hannel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency (500 kHz) for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
Soft鈭抯tart Protection for all Controllers
Under鈭扸
oltage Monitor of Supply Voltages
Over鈭扖urrent Protections for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due to
Reverse DIMM Insertion
Thermal Shutdown
20鈭扡ead 5x6 QFN Package
NCP5210 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
PIN CONNECTIONS
COMP
FBDDQ
SS
PGND
V
TT
VDDQ
AGND
FBV
TT
DDQ_REF
FB1P5
SW_DDQ
BG_DDQ
TG_TDQ
BOOT
5VDUAL
COMP_1P5
BUF_Cut
TG_1P5
BG_1P5
GND_1P5
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
ORDERING INFORMATION
Device
NCP5210MN
Package
20鈭扡ead QFN*
Shipping鈥?/div>
Rail
Tape and Reel
Typical Applications
鈥?/div>
DDR I and DDR II Memory and MCH Power Supply
NCP5210MNR2 20鈭扡ead QFN*
*5 x 6 mm
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
漏
Semiconductor Components Industries, LLC, 2003
1
December, 2003 鈭?Rev. P3
Publication Order Number:
NCP5210/D

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