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NCP5209/D Datasheet

  • NCP5209/D

  • 4-In-1 PWM Buck and Tri-Linear DDR Power Controller

  • 12頁

  • ETC

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NCP5209
Product Preview
4鈭捍n鈭? PWM Buck and
Tri鈭扡inear DDR Power
Controller
The NCP5209 4鈭捍n鈭? PWM Buck and Tri鈭扡inear Power Controller
is a complete ACPI compliant power solution for MCH and DDR
memory. This IC combines the high efficiency of a PWM controller
for the VDDQ supply with the simplicity of linear regulator for the
VTT termination voltage as well as the MCH core supply voltage.
This IC contains a synchronous PWM buck controller for driving
two external NFETs to form the DDR memory supply voltage
(VDDQ). The DDR memory termination regulator (VTT) is designed
to track at the half of reference voltage while sourcing and sinking
current. The two linear regulator controllers driving two external
NFETs are cascaded to produce the MCH core voltage (VMCH).
Protective features include, soft鈭抯tart circuitry, under鈭抳oltage
monitoring of 5VDUAL, 5VATX and 12VATX, and thermal
shutdown. The IC is packaged in a QFN鈭?0.
Features
http://onsemi.com
MARKING
DIAGRAM
20
1
20鈭扡EAD QFN
MN SUFFIX
CASE 505AB
NCP5209
AWLYYWW
1
NCP5209 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
鈥?/div>
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鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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Synchronous PWM Buck Controller for VDDQ
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
Two Linear Regulator Drivers for VMCH
All External Power MOSFETs are N鈭扖hannel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage or can be Adjusted
Externally
Fixed Switching Frequency of 250 kHz for DDQ Regulator in
Normal Mode Doubled switching frequency (500 kHz) for DDQ
Regulator in Standby Mode
Soft鈭扴tart Protection for all Regulators
Under鈭扸
oltage Monitoring of Supply Voltages
Over鈭扖urrent Protection for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Protects against Reverse DIMM Insertion
Thermal Shutdown
Housed in QFN鈭?0
PIN CONNECTIONS
COMP
FBDDQ
SS
PGND
VTT
VDDQ
AGND
FBVTT
DDQ_REF
FB1P5
SW_DDQ
BG_DDQ
TG_TDQ
BOOT
5VDUAL
OCDDQ
BUF_Cut
DRV_2P4
FB2P4
DRV_1P5
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
ORDERING INFORMATION
Device
NCP5209MN
Package
20鈭扡ead QFN*
Shipping鈥?/div>
Rail
Tape and Reel
Applications
鈥?/div>
DDR I and DDR II Memory and MCH Power Supply
NCP5209MNR2 20鈭扡ead QFN*
*5 x 6 mm
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
漏
Semiconductor Components Industries, LLC, 2003
1
December, 2003 鈭?Rev. P1
Publication Order Number:
NCP5209/D

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