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Maximum Input Clock Frequency > 3.0GHz
Maximum Input Data Rate > 5 Gb/s
425 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
LVPECL, CML or LVDS Input Compatible
Differential LVPECL Outputs, 780 mV Amplitude, Typical
Operating Range: V
CC
= 2.375 V to 3.63 V with GND = 0 V
Internal 50
W
Input Termination Provided
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP,
and SG Devices
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鈭?0擄C
to +85擄C Ambient Operating Temperature
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These are Pb鈭扚ree Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
December, 2006
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Rev. 0
1
Publication Order Number:
NB6L72/D
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