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NB6L14_07 Datasheet

  • NB6L14_07

  • 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

  • 113.83KB

  • 10頁

  • ONSEMI

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NB6L14
2.5 V/3.3 V鈥?.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi- Level Inputs with Internal Termination
http://onsemi.com
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data
fanout buffer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14 to accept various logic standards, such as
LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The
VREF_AC reference output can be used to rebias capacitor-coupled
differential or single-ended input signals. The 1:4 fanout design was
optimized for low output skew applications.
The NB6L14 is a member of the ECLinPS MAX鈩?family of high
performance clock and data management products.
Features
MARKING
DIAGRAM*
16
1
QFN-16
MN SUFFIX
CASE 485G
NB6L
14
ALYWG
G
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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Input Clock Frequency > 3.0 GHz
Input Data Rate > 2.5 Gb/s
< 20 ps Within Device Output Skew
350 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 700 mV Amplitude, Typical
LVPECL Mode Operating Range: V
CC
= 2.375 V to 3.63 V with
GND = 0 V
Internal 50
W
Input Termination Resistors Provided
VREF_AC Reference Output Voltage
-40
擄C
to +85擄C Ambient Operating Temperature
Available in 3 mm x 3 mm 16 Pin QFN
These are Pb-Free Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
Q1
IN
VT
IN
Q2
Q2
Q1
EN
D
Q
Q3
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2007
1
May, 2007 - Rev. 1
Publication Order Number:
NB6L14/D

NB6L14_07相關(guān)型號(hào)PDF文件下載

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  • 英文版
    2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
    ONSEMI
  • 英文版
    2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
    ONSEMI [ON...
  • 英文版
    2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer
    ONSEMI
  • 英文版
    2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer
    ONSEMI [ON Semi...
  • 英文版
    2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
    ONSEMI
  • 英文版
    2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
    ONSEMI [ON...
  • 英文版
    2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL...
    ONSEMI
  • 英文版
    2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL...
    ONSEMI [ON Semi...
  • 英文版
    2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
    ONSEMI
  • 英文版
    2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
    ONSEMI [ON...
  • 英文版
    2.5V / 3.3V 1:2 Differential CML Fanout Buffer
    ONSEMI [ON Semi...
  • 英文版
    2.5 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer / Translat...
    ONSEMI [ON Semi...
  • 英文版
    2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer
    ONSEMI
  • 英文版
    2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer
    ONSEMI [ON Semi...
  • 英文版
    2.5 V 1:4 AnyLevel?? Differential Input to LVDS Fanout Buffe...
    ONSEMI [ON Semi...
  • 英文版
    2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
    ONSEMI
  • 英文版
    2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
    ONSEMI [ON...
  • 英文版
    2.5 V / 3.3 V Any Differential Clock IN to Differential LVPE...
    ONSEMI
  • 英文版
    2.5 V / 3.3 V Any Differential Clock IN to Differential LVPE...
    ONSEMI [ON...
  • 英文版
    2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buff...
    ONSEMI

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