NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
http://onsemi.com
MARKING
DIAGRAM
1
The NB4N840M is a high鈭抌andwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop鈭抰hrough and protection channel switching
applications.
Internally terminated differential CML inputs accept AC鈭抍oupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50
W
input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50
W
terminations, and 400 mV output swings when
externally terminated, 50
W
to V
CC
.
Single鈭抏nded LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan鈭抩ut, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32鈭抪in QFN package.
Features
1
32
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
DA0
DA0
CML
NB4N
840M
ALYWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
0
CML
1
QA0
ENA0
SELA0
0
QA1
CML
QA1
ENA1
SELA1
QA0
DA1
DA1
CML
1
DB0
DB0
CML
0
1
QB0
CML
QB0
ENB0
SELB0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Plug鈭抜n compatible to the MAX3840 and SY55859L
Maximum Input Clock Frequency 2.7 GHz
Maximum Input Data Frequency 3.2 Gb/s
225 ps Typical Propagation Delay
80 ps Typical Rise and Fall Times
7 ps Channel to Channel Skew
430 mW Power Consumption
< 0.5 ps RMS Jitter
7 ps Peak鈭抰o鈭扨eak Data Dependent Jitter
Power Saving Feature with Disabled Outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
CML Output Level (400 mV Peak鈭抰o鈭扨eak Output), Differential
Output
鈥?/div>
These are Pb鈭扚ree Devices
0
DB1
DB1
CML
1
CML
QB1
QB1
ENB1
SELB1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
漏
Semiconductor Components Industries, LLC, 2007
1
March, 2007 鈭?Rev. 3
Publication Order Number:
NB4N840M/D
NB4N840M_07相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/...
-
英文版
3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator
-
英文版
3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
ONSEMI
-
英文版
3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
ONSEMI [ON Semi...
-
英文版
Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV an...
ONSEMI [ON Semi...
-
英文版
3.3V Differential In 1:21 Differential Fanout Clock Driver w...
ONSEMI [ON Semi...
-
英文版
3.3 V AnyLevel Receiver to CML Driver/Translator with Input ...
ONSEMI
-
英文版
3.3 V AnyLevel Receiver to CML Driver/Translator - 2.0 GHz C...
-
英文版
3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
ETC
-
英文版
3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
ONSEMI
-
英文版
3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
ETC [ETC]
-
英文版
3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer...
ONSEMI
-
英文版
NB4N527S: 3.3V 2.5Gb/s Dual AnyLevelTM to LVDS Output Driver...
-
英文版
Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV an...
ONSEMI [ON Semi...
-
英文版
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint S...
ONSEMI
-
英文版
NB4N840M Product Data Sheet
-
英文版
3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buff...
ONSEMI
-
英文版
3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buff...
ONSEMI [ON...
-
英文版
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/...
-
英文版
3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
1
2
3
4
5
6
7
8
9
