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NB4N507A Datasheet

  • NB4N507A

  • 3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer

  • 131.37KB

  • 7頁(yè)

  • ETC

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NB4N507A
3.3V/5V, 50 MHz to 200 MHz
PECL Clock Synthesizer
Description
The NB4N507A is a precision clock synthesizer which generates a
very low jitter differential PECL output clock. It produces a clock
output based on an integer multiple of an input reference frequency.
The NB4N507A accepts a standard fundamental mode crystal,
using Phase鈭扡ocked鈭扡oop (PLL) techniques, will produce output
clocks up to 200 MHz. In addition, the PLL circuitry will produce a
50% duty cycle square鈭抴ave clock output.
The NB4N507A can be programmed to generate a selection of input
reference frequency multiples. An exact 155.52 MHz output clock can
be generated from a 19.44 MHz crystal and the x8 multiplier selection.
The NB4N507A is intended for low output jitter clock generation.
Features
http://onsemi.com
MARKING
DIAGRAM
16
NB4N507A
AWLYWW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Input Crystal Frequency of 10
鈭?/div>
27 MHz
Enable Usage of Common Low鈭扖ost Crystal
Differential PECL Output Clock Frequencies up to 200 MHz
Duty Cycle of 48%/52%
Operating Range: V
CC
= 3.0 V to 5.5 V
Ideal for SONET Applications and Oscillator Manufacturers
Available in Die Form
Packaged in 16鈭扨in Narrow SOIC
Pb鈭扚ree Packages are Available*
SOIC鈭?6
D SUFFIX
CASE 751B
A
WL, L
Y
WW, W
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Osc
PD
CP
VCO
Mult
PECL
CLKOUT
CLKOUT
OE
S0 S1
Figure 1. Simplified Logic Block
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
錚?/div>
Semiconductor Components Industries, LLC, 2005
March, 2005
鈭?/div>
Rev. 0
1
Publication Order Number:
NB4N507A/D

NB4N507A相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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  • 英文版
    3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/...
    ON SEMICONDUCTOR
  • 英文版
    3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator
    ON SEMICONDUCTOR
  • 英文版
    3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
    ONSEMI
  • 英文版
    3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
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    Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV an...
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  • 英文版
    3.3V Differential In 1:21 Differential Fanout Clock Driver w...
    ONSEMI [ON Semi...
  • 英文版
    3.3 V AnyLevel Receiver to CML Driver/Translator with Input ...
    ONSEMI
  • 英文版
    3.3 V AnyLevel Receiver to CML Driver/Translator - 2.0 GHz C...
    ON SEMICONDUCTOR
  • 英文版
    3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
    ETC
  • 英文版
    3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
    ONSEMI
  • 英文版
    3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer
    ETC [ETC]
  • 英文版
    3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer...
    ONSEMI
  • 英文版
    NB4N527S: 3.3V 2.5Gb/s Dual AnyLevelTM to LVDS Output Driver...
    ON SEMICONDUCTOR
  • 英文版
    Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV an...
    ONSEMI [ON Semi...
  • 英文版
    3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint S...
    ONSEMI
  • 英文版
    NB4N840M Product Data Sheet
    ON SEMICONDUCTOR
  • 英文版
    3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buff...
    ONSEMI
  • 英文版
    3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buff...
    ONSEMI [ON...
  • 英文版
    3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/...
    ON Semiconductor
  • 英文版
    3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Diffe...
    ON Semiconductor

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