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NB3N502DR2G Datasheet

  • NB3N502DR2G

  • 14 MHz to 190 MHz PLL Clock Multiplier

  • 5頁(yè)

  • ONSEMI

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NB3N502
14 MHz to 190 MHz PLL
Clock Multiplier
Description
The NB3N502 is a clock multiplier device that generates a low jitter,
TTL/CMOS level output clock which is a precise multiple of the
external input reference clock signal source. The device is a cost
efficient replacement for the crystal oscillators commonly used in
electronic systems. It accepts a standard fundamental mode crystal or
an external reference clock signal. Phase鈭扡ocked鈭扡oop (PLL) design
techniques are used to produce an output clock up to 190 MHz with a
50% duty cycle. The NB3N502 can be programmed via two select
inputs (S0, S1) to provide an output clock (CLKOUT) at one of six
different multiples of the input frequency source, and at the same time
output the input aligned reference clock signal (REF).
Features
http://onsemi.com
MARKING DIAGRAM
8
1
SOIC鈭?
D SUFFIX
CASE 751
3N502
A
L
Y
W
G
8
3N502
ALYW
G
1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Clock Output Frequency up to 190 MHz
Operating Range: V
DD
= 3 V to 5.5 V
Low Jitter Output of 15 ps One Sigma (rms)
Zero ppm Clock Multiplication Error
45% 鈭?55% Duty Cycle
25 mA TTL鈭抣evel Drive Outputs
Crystal Reference Input Range of 5 鈭?27 MHz
Input Clock Frequency Range of 2 鈭?50 MHz
Available in 8鈭抪in SOIC Package or in Die Form
Full Industrial Temperature Range 鈭?0擄C to 85擄C
This is a Pb鈭扚ree Device
V
DD
ORDERING INFORMATION
Device
NB3N502DG
NB3N502DR2G
Package
SOIC鈭?
(Pb鈭扚ree)
SOIC鈭?
(Pb鈭扚ree)
Shipping
鈥?/div>
98 Units/Rail
2500/Tape & Reel
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Reference
Clock
TTL/
CMOS
Output
REF
X1/CLK
X2
Crystal
Oscillator
Multiplier
Select
梅
P
Phase
Detector
Charge
Pump
VCO
TTL/
CMOS
Output
CLKOUT
梅
M
S1 S0
GND
Feedback
Figure 1. NB3N502 Logic Diagram
漏
Semiconductor Components Industries, LLC, 2006
1
March, 2006 鈭?Rev. 0
Publication Order Number:
NB3N502/D

NB3N502DR2G 產(chǎn)品屬性

  • 2,500

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器

  • -

  • PLL 時(shí)鐘乘法器

  • 帶旁路

  • 時(shí)鐘，晶體

  • CMOS，TTL

  • 1

  • 1:2

  • 無(wú)/無(wú)

  • 190MHz

  • 是/是

  • 3 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 8-SOIC（0.154"，3.90mm 寬）

  • 8-SOICN

  • 帶卷 (TR)

NB3N502DR2G相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    14 MHz to 190 MHz PLL Clock Multiplier
    ONSEMI
  • 英文版
    14 MHz to 190 MHz PLL Clock Multiplier
    ONSEMI [ON Semi...
  • 英文版
    3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
    ONSEMI
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    3.3V, Crystal - To- HCSL Clock Generator
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  • 英文版
    IC LL CLOCK MULTIPLIER 8SOIC
  • 英文版
    14 MHz to 190 MHz PLL Clock Multiplier
    ON Semiconductor
  • 英文版
    14 MHz to 190 MHz PLL Clock Multiplier
    ONSEMI
  • 英文版
    IC CLK MULTIPLIER PLL 8-SOIC
  • 英文版
    14 MHz to 190 MHz PLL Clock Multiplier
    ONSEMI [ON Semi...
  • 英文版
    IC PLL CLOCK MULTIPLIER 8-SOIC
  • 英文版
    3.3 V / 5.0 V Ultra−Low Skew 1:4 Clock Fanout Buffer
    ON Semiconductor

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