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NB100LVEP222FAR2 Datasheet

  • NB100LVEP222FAR2

  • 2.5 V/3.3 V 1:15 Differential ECL/PECL ±1/±2 Clock Driver

  • 10頁

  • ONSEMI

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NB100LVEP222
2.5 V/3.3 V 1:15 Differential
ECL/PECL
梅1/梅2
Clock Driver
The NB100LVEP222 is a low skew 1:15 differential
梅1/梅2
ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be used in a differential
configuration or single鈭抏nded (with V
BB
output reference bypassed
and connected to the unused input of a pair). Either of two fully
differential clock inputs may be selected. Each of the four output
banks of 2, 3, 4, and 6 differential pairs may be independently
configured to fanout 1X or 1/2X of the input frequency. When the
output banks are configured with the
B1
mode, data can also be
distributed. The LVEP222 specifically guarantees low output to output
skew. Optimal design, layout, and processing minimize skew within a
device and from lot to lot. This device is an improved version of the
MC100LVE222 with higher speed capability and reduced skew.
The fsel pins and CLK_Sel pin are asynchronous control inputs.
Any changes may cause indeterminate output states requiring an MR
pulse to resynchronize any 1/2X outputs (See Figure 3). Unused
output pairs should be left unterminated (open) to reduce power and
switching noise.
The NB100LVEP222, as with most ECL devices, can be operated
from a positive V
CC
/V
CC0
supply in LVPECL mode. This allows the
LVEP222 to be used for high performance clock distribution in
+2.5/3.3 V systems. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. For more information on using PECL, designers should refer
to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single鈭抏nded LVPECL input conditions, the
unused differential input is connected to V
BB
as a switching reference
voltage. V
BB
may also rebias AC coupled inputs. When used, decouple
V
BB
and V
CC
/V
CC0
via a 0.01
mF
capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, V
BB
should be left open.
Single鈭抏nded CLK input operation is limited to a V
CC
/V
CC0
鈮?/div>
3.0 V in
LVPECL mode, or V
EE
v
鈭?.0 V in NECL mode.
http://onsemi.com
MARKING
DIAGRAM*
52鈭扡EAD LQFP
THERMALLY ENHANCED
CASE 848H
FA SUFFIX
A
WL
YY
WW
G
NB100
LVEP222
AWLYYWWG
52
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP222FA
Package
LQFP鈭?2
Shipping鈥?/div>
160 Units/Tray
NB100LVEP222FAR2 LQFP鈭?2 1500/Tape & Reel
NB100LVEP222FAG
LQFP鈭?2
(Pb鈭扚ree)
160 Units/Tray
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
20 ps Output鈭抰o鈭扥utput Skew
85 ps Part鈭抰o鈭扨art Skew
Selectable 1x or 1/2x Frequency Outputs
NB100LVEP222FARG LQFP鈭?2 1500/Tape & Reel
(Pb鈭扚ree)
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
LVPECL Mode Operating Range:
V
CC
/V
CC0
= 2.375 V to 3.8 V with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range:
V
CC
/V
CC0
= 0 V with V
EE
= 鈭?.375 V to 鈭?.8 V
鈥?/div>
Internal Input Pulldown Resistors
鈥?/div>
Performance Upgrade to ON Semiconductor鈥檚 MC100LVE222
鈥?/div>
V
BB
Output
鈥?/div>
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2005
1
October, 2005鈭?Rev. 9
Publication Order Number:
NB100LVEP222/D

NB100LVEP222FAR2 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器

  • 100LVEP

  • 扇出緩沖器（分配），除法器，多路復(fù)用器

  • 1

  • 1:15

  • 是/是

  • LVECL，LVPECL

  • LVECL，LVPECL

  • 1GHz

  • ±2.375 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 52-LQFP 裸露焊盤

  • 52-LQFP（10x10）

  • 剪切帶 (CT)

  • NB100LVEP222FOSCT

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