NB100LVEP222
2.5V/3.3V 1:15 Differential
ECL/PECL
梅1/梅2
Clock Driver
The NB100LVEP222 is a low skew 1:15 differential
梅1/梅2
ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be used in a differential
configuration or single-ended (with V
BB
output reference bypassed
and connected to the unused input of a pair). Either of two fully
differential clock inputs may be selected. Each of the four output
banks of 2, 3, 4, and 6 differential pairs may be independently
configured to fanout 1X or 1/2X of the input frequency. The LVEP222
specifically guarantees low output to output skew. Optimal design,
layout, and processing minimize skew within a device and from lot to
lot. This device is an improved version of the MC100LVE222 with
higher speed capability and reduced skew.
The fsel pins and CLK_Sel pin are asynchronous control inputs.
Any changes may cause indeterminate output states requiring an MR
pulse to resynchronize any 1/2X outputs (See Figure 3). Unused
output pairs should be left unterminated (open) to reduce power and
switching noise.
The NB100LVEP222, as with most ECL devices, can be operated
from a positive V
CC
supply in LVPECL mode. This allows the
LVEP222 to be used for high performance clock distribution in
+2.5/3.3 V systems. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. For more information on using PECL, designers should refer
to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single- ended LVPECL input conditions, the
unused differential input is connected to V
BB
as a switching reference
voltage. V
BB
may also rebias AC coupled inputs. When used, decouple
V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or
sinking to 0.5 mA. When not used, V
BB
should be left open.
Single- ended CLK input operation is limited to a V
CC
鈮?/div>
3.0 V in
LVPECL mode, or V
EE
v
-3.0 V in NECL mode.
http://onsemi.com
MARKING
DIAGRAM*
NB100
LVEP222
AWLYYWW
52-LEAD LQFP
THERMALLY ENHANCED
CASE 848H
FA SUFFIX
A
WL
YY
WW
52
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP222FA
Package
LQFP-52
Shipping
160 Units/Tray
NB100LVEP222FAR2 LQFP-52 1500/Tape & Reel
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
20 ps Output-to-Output Skew
85 ps Part-to-Part Skew
Selectable 1x or 1/2x Frequency Outputs
LVPECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= -2.375 V to -3.8 V
鈥?/div>
Internal Input Pulldown Resistors
鈥?/div>
Performance Upgrade to ON Semiconductor鈥檚 MC100LVE222
鈥?/div>
V
BB
Output
漏
Semiconductor Components Industries, LLC, 2003
1
January, 2003- Rev. 8
Publication Order Number:
NB100LVEP222/D
NB100LVEP222/D相關型號PDF文件下載
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