NB100LVEP17
2.5V / 3.3V / 5V ECL Quad
Differential Driver/Receiver
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
http://onsemi.com
MARKING
DIAGRAMS*
20
1
20
N100
LP17
ALYW
1
24
1
24
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
TSSOP-20
DT SUFFIX
CASE 948E
PECL Mode Operating Range: V
CC
= 2.375 V to 5.5 V
with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= -2.375 V to -5.5 V
鈥?/div>
Q Output Will Default LOW with Inputs Open or at V
EE
24 PIN QFN
MN SUFFIX
CASE 485L
A
L
Y
W
N100
LP17
ALYW
鈥?/div>
V
BB
Output
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP17DT
Package
TSSOP-20
Shipping
75 Units/Rail
NB100LVEP17DTR2 TSSOP-20 2500/Tape & Reel
NB100LVEP17MN
NB100LVEP17MNR2
QFN-24
QFN-24
92 Units/Rail
3000/Tape & Reel
漏
Semiconductor Components Industries, LLC, 2003
1
April, 2003 - Rev. 4
Publication Order Number:
NB100LVEP17/D
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