鈥?/div>
Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9鈥揵it
bidirectional latchable transceivers and are
intended to provide the electrical interface to
a high performance wired鈥揙R bus. The B
port inverting drivers are low鈥揷apacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a precision band
gap references for improved noise margins.
The B port interfaces to 鈥橞ackplane
Transceiver Logic鈥?(BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching is employed, there-
fore BTL propagation delays are short. Al-
though the voltage swing is much less for
BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8965 and 74F8966 A ports have TTL
3鈥搒tate drivers and TTL receivers.
The B ports have standard BTL I/O with
100mA current sink capability. The B鈥搕o鈥揂
path is a simple inverted buffered path. When
going from A鈥搕o鈥揃 the user may choose be-
tween a buffered path or a latching function.
The 74F8966 also has an idle arbitrator/multi-
ple competitors output. The IAMC output
compares, using a wired鈥揙R configuration,
the data on the bus to the latched data pres-
ented to the bus. If the bus data matches the
data presented by the 74F8966 then IAMC is
high. If the data doesn鈥檛 match then IAMC
goes low.
TYPICAL PROPAGATION DELAY
3.5ns
3.5ns
TYPICAL SUPPLY CURRENT( TOTAL)
80mA
80mA
ORDERING INFORMATION
DESCRIPTION
44鈥損in PLCC
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
鹵
10%, T
amb
= 0
擄
C to +70
擄
C
N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
A0 鈥?A8
B0 鈥?B8
OEA, OEB0, OEB1
LS
IAREQ
LE
A0 鈥?A8
B0 鈥?B8
IAMC
TTL data inputs
Data inputs with threshold circuitry
Output enable inputs
Latch select (active low) (鈥橣8965)
Idle arbitration request (active low) (鈥橣8965)
Latch enable input (active low)
3鈥搒tate TTL outputs
Open collector BTL outputs
Idle arbitration/multiple competitors output (鈥橣8966)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.033
5.0/0.167
1.0/0.167
1.0/0.167
1.0/0.167
1.0/0.167
150/40
OC/166.7
OC/80
LOAD VALUE
HIGH/LOW
20碌A(chǔ)/20碌A(chǔ)
100碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/100碌A(chǔ)
3mA/24mA
OC/100mA
OC/48mA
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the high state and 0.6mA in the low state.
2. OC = Open collector.
December 19, 1990
1
853 1526 01320
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