equivalent load impedances down to 10鈩?/div>
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching to 9鈩?is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
The 74F8963 is the non-inverting version of
74F8962.
鈥?/div>
High drive (100mA) open collector drivers
on B port
DESCRIPTION
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
The B port interfaces to 鈥楤ackplane
Transceiver Logic鈥?(BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
鈥?/div>
Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
鈥?/div>
High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
鈥?/div>
Compatible with IEEE 896 futurebus
standards
鈥?/div>
Built鈥搃n precision band鈥揼ap reference
provides accurate receiver thresholds and
improved noise immunity
TYPE
74F8962
74F8963
TYPICAL PROPAGATION DELAY
6.5ns
5.5ns
TYPICAL SUPPLY CURRENT( TOTAL)
90mA
90mA
ORDERING INFORMATION
DESCRIPTION
44鈥損in Quad Flat Pack
1
44鈥損in Plastic Leaded Chip Carrier
Note to ordering information
1. Flatpack package is not available at this time.
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
鹵
10%, T
amb
= 0
擄
C to +70
擄
C
N74F8962Y, N74F8963Y
N74F8962A, N74F8963A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
AI0 鈥?AI8
B0 鈥?B8
OEAB, OEBA
LEAB, LEBA
AO0 鈥?AO8
PNP latched inputs
Data inputs with threshold circuitry
Output enable inputs (active low)
Latch enable inputs (active low)
3鈥搒tate outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.167
5.0/0.167
1.0/0.033
1.0/0.033
150/40
OC/166.7
LOAD VALUE
HIGH/LOW
20碌A(chǔ)/100碌A(chǔ)
100碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/20碌A(chǔ)
20碌A(chǔ)/20碌A(chǔ)
3mA/24mA
OC/100mA
B0 鈥?B8
Open collector outputs
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the high state and 0.6mA in the low state.
2. OC = Open collector.
March 11, 1993
1
853鈥?425 09230
N74F8963Y相關(guān)型號PDF文件下載
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英文版
Quad 2-input NAND gate
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