equivalent load impedances down to 10鈩?/div>
DESCRIPTION
The 74F8960 and 74F8961 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired鈥揙R bus. The B
port inverting drivers are low鈥揷apacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 100 mV
threshold region and a 4ns glitch filter.
The B port interfaces to 鈥楤ackplane
Transceiver Logic鈥?(BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident switching is employed, therefore BTL
propagation delays are short. Although the
voltage swing is much less for BTL, so is its
receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8960 and 74F8961 A ports have TTL
3鈥搒tate drivers and TTL receivers with a latch
function. A separate High鈥搇evel control input
(VX) is provided to limit the A side output
level to a given voltage level (such as 3.3V).
For 5.0V systems, VX is simply tied to VCC.
The 74F8961 is the non鈥搃nverting version of
74F8960.
鈥?/div>
High drive (100mA) open collector drivers
on B port
鈥?/div>
Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
鈥?/div>
High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
鈥?/div>
Compatible with IEEE futurebus standards
鈥?/div>
Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
鈥?/div>
Controlled output ramp and multiple GND
pins minimize ground bounce
鈥?/div>
Glitch-free power up/down operation
TYPE
74F8960
74F8961
TYPICAL PROPAGATION DELAY
6.5ns
6.5ns
TYPICAL SUPPLY CURRENT( TOTAL)
80mA
80mA
ORDERING INFORMATION
DESCRIPTION
28鈥損in plastic DIP (300 mil)
1
28鈥損in PLCC
1
NOTE:
Thermal mounting techiques are recommended.
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
鹵
10%, T
amb
= 0
擄
C to +70
擄
C
N74F8960N, N748961N
N74F8960A, N74F8961A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
A0 鈥?A8
B0 鈥?B8
OEA
OEB0, OEB1
LE
A0 鈥?A7
PNP latched inputs
Data inputs with threshold circuitry
A output enable input (active high)
B output enable inputs (active low)
Latch enable input (active low)
3鈥搒tate outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
3.5/0.117
5.0/0.167
1.0/0.033
1.0/0.033
1.0/0.033
150/40
OC/166.7
LOAD VALUE
HIGH/LOW
70碌A(chǔ)/70碌A(chǔ)
100碌A(chǔ)/100碌A(chǔ)
20碌A(chǔ)/20碌A(chǔ)
20碌A(chǔ)/20碌A(chǔ)
20碌A(chǔ)/20碌A(chǔ)
3mA/24mA
OC/100mA
B0 鈥?B7
Open collector outputs
NOTES:
1. One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the high state and 0.6mA in the low state.
2. OC = Open collector.
December 19, 1990
1
853-1120 01322
N74F8960相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠(chǎng)商
下載
-
英文版
Quad 2-input NAND gate
PHILIPS
-
英文版
Quad 2-input NAND gate
PHILIPS [P...
-
英文版
Quad 2-input NAND gate
PHILIPS
-
英文版
Quad 2-input NAND gate
PHILIPS [P...
-
英文版
Quad 2-input NOR gate
PHILIPS
-
英文版
Quad 2-input NOR gate
PHILIPS [P...
-
英文版
Quad 2-input NOR gate
PHILIPS
-
英文版
Quad 2-input NOR gate
PHILIPS [P...
-
英文版
Hex inverter
PHILIPS
-
英文版
Hex inverter
PHILIPS [P...
-
英文版
Hex inverter
PHILIPS
-
英文版
Hex inverter
PHILIPS [P...
-
英文版
Inverter/buffer drivers
PHILIPS
-
英文版
Inverter/buffer drivers
PHILIPS [P...
-
英文版
Inverter/buffer drivers
PHILIPS
-
英文版
Inverter/buffer drivers
PHILIPS [P...
-
英文版
Inverter/buffer drivers
PHILIPS
-
英文版
Inverter/buffer drivers
PHILIPS [P...
-
英文版
Inverter/buffer drivers
PHILIPS [P...
-
英文版
Inverter/buffer drivers
PHILIPS
1
2
3
4
5
6
7
8
9
10
11
