鈥?/div>
High speed parallel registers with
this device only on the output states.
Both OE pins are enabled low.
All operating modes, other than clear,
3鈥揝tate, and the two hold modes re-
quire the rising edge of the clock. All
setup and hold times must be observed
for proper functioning.
Data on the internal register can be
switched on either the A or B ports for
output.
Depeding on the state of the select in-
puts (S0, S1, S2), and carry in/ serial in/
clock enable (CI/SI/CE), the 74F807 has
nine distinct operating modes:
1. Add mode w/carry in 鈥?the CI/SI/CE
input is used as a carry in signal and the
STATOUT output is the carry out signal.
(In add mode the COUT is NOT
registered. This means the carry output
signal appears at the STATOUT output
one clock prior to the related data.). In
this mode, the CI/SI/CE input is added
to the register contents and to the
inputs. (The adder uses only the An
inputs, not the Bn inputs.)
2. Add mode wo/carry in 鈥撯€?same as above
except the CI/SI/CE input is not included in
the addition.
3. Count w/count enable (count) 鈥撯€?the CI/SI/
CE input is now used as the count enable
positive edge鈥搕riggered D鈥搕ype
flip鈥揻lops
鈥?/div>
High speed full adder
input and the STATOUT output is terminal
count. In this mode the CI/SI/CE input must
be high to enable the count function. The
register contents are incremented by one.
4. Count w/count enable (hold) 鈥撯€?same as
above except no incrementing occurs.
5. Count wo/count enable 鈥撯€?same as num-
ber 3 except the CI/SI/CE input has no con-
trol over counting or holding.
6. Shift 鈥撯€?The CI/SI/CE input now becomes
the serial input and the STATOUT output
becomes the serial output. In this mode the
CI/SI/CE input is shifted into the Q0 register,
Q0 into the Q1 register etc. The Q7 register
is shifted into the STATOUT.
7. Load A inputs 鈥撯€?The CI/SI/CE input has
no bearing in either of the load modes. The
STATOUT output becomes the parity out.
The parity out is high for an odd number of
registered bits high, and low for even number
of registered bits high (even parity). In this
mode the An inputs are loaded into the
internal register and output to the B bus. If
OEA = low the internal register would wrap
around and be loaded again.
8. Load B inputs 鈥撯€?same as number 7
except the A and B busses are switched.
9. Hold 鈥撯€?Again the CI/SI/CE input is not
used; the STATOUT output is still the parity
out. In this mode either the A bus, B bus or
both can be held with the registered data. No
other operation is performed.
鈥?/div>
8鈥揵it parity generator
鈥?/div>
High impedance PNP inputs for light
bus loading
鈥?/div>
Center V
CC
and GND pins and con-
trolled output buffers minimize
ground鈥揵ounce problems
鈥?/div>
3鈥揝tate glitch鈥揻ree power鈥搖p and
power鈥揹own
鈥?/div>
Broadside pinout
DESCRIPTION
The 74F807 is a registered transceiver
that also has the capability to perform
count, shift, and add functions. It is also
has the capability to generate a parity
bit output. All of this is done within a
28鈥損in package.
The MR input is an overriding
asynchronous reset which forces the
STATOUT output low as well as the A
and B busses.
The A and B busses have separate OE
inputs (OEA, OEB]. These inputs have
no bearing on the internal functioning of
TYPE
74F807
TYPICAL f
max
115MHz
TYPICAL SUPPLY CURRENT (TOTAL)
155mA
ORDERING INFORMATION
DESCRIPTION
28鈥損in plastic DIP (300 mils)
28鈥損in SOL
1
28鈥損in PLCC
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
鹵
10%, T
amb
= 0
擄
C to +70
擄
C
N74F807N
N74F807D
N74F807A
Note to ordering information
1.Thermal
mounting techiques are recommended. See SMD Process Applications (page 17) for a discussion of thermal consideration for surface
mounted devices.
June 18, 1991
1
853鈥?421 02931
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