Philips Semiconductors
Product specification
Dual 1-of-4 decoder (3-State)
74F539
DESCRIPTION
The 74F539 contains two independent decoders. Each accepts two
address (A0 - A1) input signals and decodes them to select one of
four mutually exclusive outputs. A Polarity control (P) input
determines whether the outputs are active Low (P=H) or active High
(P=L). An active-Low Enable (E) is available for data demultiplexing.
Data is routed to the selected output in non-inverted or inverted form
in the active-Low mode or inverted form in the active-High mode. A
High signal on the Output Enable (OEn) input forces the 3-State
outputs to the high impedance state.
TYPICAL SUPPLY
CURRENT
(TOTAL)
40mA
PIN CONFIGURATION
Q2b
Q1b
Q0b
Pb
OEb
A0a
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q3b
18 A1b
17 A0b
16 Eb
15 Ea
14 OEa
13 Pa
12 Q0a
11 Q1a
TYPE
74F539
TYPICAL
PROPAGATION DELAY
7.5ns
A1a
Q3a
Q2a
GND 10
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic DIP
20-Pin Plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F539N
N74F539D
SF01013
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0a - A1a
A0b - A1b
Ea, Eb
OEa, OEb
Pa, Pb
Q0a鈥換3a
Q0b鈥換3b
Decoder A Address inputs
Decoder B Address inputs
Enable inputs (active Low)
Output Enable inputs (active Low)
Polarity control inputs
Decoder A Data outputs
Decoder A Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
150/40
LOAD VALUE
HIGH/LOW
20碌A/0.6mA
20碌A/0.6mA
20碌A/0.6mA
20碌A/0.6mA
20碌A/0.6mA
3.0mA/24mA
3.0mA/24mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20碌A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
6
7
17
18
LOGIC SYMBOL (IEEE/IEC)
DMUX
A0a
A1a
A0b
A1b
4
5
17
18
16
13
14
6
0
1
G
0
3
N4
0,4
EN
1,4
2,4
3,4
2
1
19
3
13
15
14
4
16
5
Pa
Ea
OEa
Pb
Eb
OEb
Q0a
Q1a
12
11
9
8
Q2a
Q3a
Q0b Q1b
Q2b
Q3b
7
15
V
CC
= Pin 20
GND = Pin 10
12
11
9
8
3
2
1
19
SF01014
SF01015
1990 Feb 23
1
853鈥?274 98905
1
2
3
4
5
