鈥?/div>
Cascadable in word鈥搘idth and depth
direction
TYPICAL
SUPPLY
CURRENT
(TOTAL)
90mA
DESCRIPTION
This 64-bit active element First-In-First-Out
(FIFO) is a monolithic Schottky-clamped
transistor-transistor logic (STLL) array
organized as 16 words of 4-bits each. A
memory system using the 74F224 can be
easily expanded in multiples of 15m+1 words
or of 4n bits, or both (where n is the number
of packages in the horizontal array).
However, an external gating is required (see
Figure 1). For longer words using 74F224,
the IR signals of the first-rank packages and
OR signals of the last-rank packages must be
ANDed for proper synchronization.The
3-State outputs controlled by a single input
(OE) make bus connection and multiplexing
easy.
TYPE
TYPICAL
f
max
50MHz
74F224
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
鹵
10%, T
amb
= 0
擄
C to +70
擄
C
16-pin plastic Dual In-line Package
16-pin plastic Small Outline Large
N74F224N
N74F224D
0406C
0171B
DRAWING NUMBER
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
LDCP
D0 鈥?D3
OE
UNCP
MR
IR
Q0 鈥?Q3
Load clock input
Data inputs
Output enable input (active high)
Unload clock input
Master reset input (active low)
Input ready output
Data outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
50/33
50/33
LOAD VALUE
HIGH/LOW
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
OR
Output ready output
NOTE TO INPUT AND OUTPUT LOADING AND FAN OUT TABLE
1. One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the high state and 0.6mA in the low state.
PIN CONFIGURATION
LOGIC SYMBOL
4
5
6 7
IED/IEEE SYMBOL
FIFO 16 X 4
1
9
EN5
CT=0
CT<0
CTR
&
+/C1
Z2
CT>0
15
4
1D
5
&
鈥?CT=0
2
Z3
&
V4
4,5
13
12
13
10
2
3
2
14
OE 1
IR
2
16
15
14
13
12
11
10
9
V
CC
UNCP
OR
Q0
Q1
Q2
Q3
13 12 11 10 2 14
MR
V
CC
= Pin 16
GND = Pin 8
1
13
3
9
OE
UNCP
LDCP
MR
Q0 Q1 Q2 Q3 IR OR
D0 D1 D2 D3
LDCP 3
D0
D1
D2
D3
GND
4
5
6
7
8
3
6
7
September 7, 1990
1
1
